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AB-1205-5
4 Port Cascadeable 100base and ATM Repeater Hub
AB-1205-5 4-Port 100baseTX Repeater
Product Specification
AB Semicon AB1205-5 100base and ATM Repeater Hub Product Specification
Copyright (c) Copyright 1997 AB Semicon Limited. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or any computer language, in any form or by any third party, without the prior written permission of AB Semicon Limited.
Disclaimer AB Semicon Limited reserves the right to revise this publication and to make changes from time to time to the contents hereof without obligation to notify any person or organization of such revision or changes. AB Semicon Limited has endeavoured to ensure that the information in this publication is correct, but will not accept liability for any error or omission.
-2-
rev 1.4
AB-1205-5
100base and ATM 4 Port Repeater
Features: * * * * * * 4 ports for or AMD's FDDI chip sets and GECs NWK914 Local bi-directional high-speed bus for daisychaining Compatible with 100base TX, T4 and T6 Compatible with 100base VG 80 pin PQFP package Low Power C-Mos Technology 0.8micron
rev 1.4 - 3 -
INTRODUCTION This repeater chip allows the connection of an AMD 79865 and 79866 chipset together with NSM DP83223 as the Physical Layer chip as well as being able to use the GEC NWK 914 or AB Semicon AB10100PHY which can replace the AMD and National chip set giving a maximum in flexibility. It can process 4 ports simultaneously in half duplex. The encryption and decryption circuit is built into each of the channels. A local bus allows daisychaining of any number of devices. Chip Structure The chip contains four high-speed 5bit channels and the control logic for the physical layer interface. Each channel has its own encryption and decryption circuit for circuit simplicity and reduced EMI. Error arbitration logic and collision detection which is also available on output pins on the chip which are capable of driving LEDs directly. There are additional LED outputs to indicate TX or RX data.
Global Reset Packet Management Logic and Timers
Idle Detect
Daisychain
control In/Out
LED Output
RX-1 Input RX-2 Input RX-3 Input RX-4 Input Cypherstream Decryption Cypherstream Decryption Cypherstream Decryption Cypherstream Decryption Ring Buffer Ring Buffer Ring Buffer Ring Buffer Priority Packet Switch Logic & Idle Byte Insertion for Active Channel
Cypherstream Encryption Cypherstream Encryption Cypherstream Encryption Cypherstream Encryption
TX-1 Output TX-2 Output TX-3 Output TX-4 Output Daisychain In/Output
Note:
Daisychain Control and Data I/O are only functional on AB-1205-5
Figure 1 Functional Block Diagram
-4-
rev 1.4
APPLICATIONS The chip can be used in many different applications where random encryption and decryption is required to achieve a semi spread spectrum use of copper wire to reduce RFI emitted from the cable. It is most powerful for repeater devices such as 4, 8 or 16 port or any multiple of 4 ports, HUB devices. Such applications include 100baseTX repeaters. Figure 2 gives an overview of low cost repeater applications for which this chip is suitable. Such a repeater can be used in Workgroup or Serverbased environments. The data is fully transparently distributed through the Network. 100baseTX Repeater HUB
100baseTX Fileserver
100baseTX LaserPrinter
100baseTX Workstation
Figure 2
EXAMPLE for a 4 Port Repeater Figure 3 shows a 4 port repeater with an extension connector to daisychain any number of 4 port repeaters.
AM 79865
XTAL OSC
~
O AB-1205-1 or
AB-1205-5
4-Port Repeater
O O O
12 way daisychain connector (AB-1205-5 only)
AM 79866
O
DP 83223
magnetics magnetics
TX
RX
RJ 45 connector
TX
RX
RJ 45 connector
TX
RX
RJ 45 connector
TX
RX
RJ 45 connector
Figure 3
rev 1.4 - 5 -
Interconnection of AB1205-5 and AB10100PHY Physical Layer The diagram below shows how the signals between AB1205-5 and AB10100PHY are interconnected for a single port. This interconnection is repeated for the remaining 3 ports, please also refer to the AB10100PHY Product Specification.
1KW
Xial Osc.
100pF
.033mF 620W 50W
TXVCC 50W 0.1mF 1:1 M A G N E T I C S
a LFTA
AB 1205-5
PCS or MAC (with embedded PCS)
REFCLK TDAT0-4
LFT8 TXREF TXGND TXOP
5 a a 5
TXC RXC RDAT0-4 LFRA
AB 10/100 PHY
LFR8
TXON
RXIP RXIN
15W 68W 15W
RJ45
0.1mF 6.2KW
Fig 6. Connection of AB10/100PHY to AB1205-5
-6-
rev 1.4
Clock Distribution Circuit The following diagram shows how the clock is distributed. To assure that the clock is arriving at the same time on all channels, a 244 is used to re-shape the clock signal for each channel.
AB1205-5
LSCLK
LNKOK2 RSCLK2
25MHz C11 100nF 50v VCC R13 24R 29 R10 2 4 6 8 11 13 15 17 GND 1A1 1A2 1A3 1A4 2A1 2A2 2A3 3A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 18 16 14 12 9 7 5 3 24R X X X X X
RSCLK2
GND Shield power & ground
AB10100 PHY
LNKOK2
VCC R14 10K
RX2IN0 RX2IN1 RX2IN2 RX2IN3 RX2IN4 TX2OUT4 TX2OUT3
31 32 33 34 35 77 76
RX2IN0 RX2IN1 RX2IN2 RX2IN3 RX2IN4 TX2OUT4 TX2OUT3
AB1205-5
R X 2 I N(0..4)
TX2 TX2 TX2 OUT0 OUT1 OUT2
T X 2 O U T 0 T X 2 O U T 1 T X 2 O U T 2
1 19
TX2IN(0..4)
Diagram showing clock distribution Note: When daisychaining the AB1205-5 the remaining buffers of the 244 may be used to re-generate the clock signal.
21 21 21 21 21
244
RX2IN(0..4)
TX2IN(0..4)
21 21 21 21 21 21 21 21
LSCLK
rev 1.4 - 7 -
Reset circuitry for AB-1205-5 The following diagram shows the reset circuit for the AB-1205-5 four port and cascadeable hub chip.
Pin 53
______ RESET AB-1205-5
Reset Circuit for AB-1205-5
to other devices
DISAB(1) Collision Relay 55 57 65 AB-1205-5 64 63 61 60 54 AS244/2 OSC~ 25Mhz RX_BUSY_0 DAISY<4> DAISY<3> DAISY<2> DAISY<1> DAISY<0>
55 57 65 64 63 61 60 AS244/1 54 AB-1205-5
Daisychaining the AB-1205-5
-8-
rev 1.4
Thermal Characteristics for AB1205-5 This device is supplied in a plastic Quad Flat Pack with a pin count of 80. In this configuration, it has a thermal resistance (0 JA - Junction-to-Ambient Measurement) of 85 C/W in an Alloy 42 Lead Frame with a value of 68 C/W in a Copper Lead Frame. As this device is currently supplied in the Alloy Lead Frame, only that figure has been used in the following calculations. The Power Dissipation (Pd) of the device is calculated as follows: Pd + TJ - TA 0JA Thus the Power Dissipation is 1.2 Watts at an ambient of 25 C and 650 mW at 70 C. The following plot shows the variation of Power Dissipation with ambient: Power Dissipation of AB1205-5 typical 300mW
1.6 1.4 1.2 1-
0.2 -20 -10 0-
100 -
110 -
120 -
125 -
130 -
Ta
Maximum ambient temperature
A value of TJ max of 125 C was used. The range of TJ is -40 to 125 C.
rev 1.4 - 9 -
140 -
10 -
20 -
30 -
40 -
50 -
60 -
70 -
80 -
90 -
0-
5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321 5432121098765432109876543210987654321
AB1205-5 typical
Pd
0.8 0.6 0.4 -
Recommended area of operation
Packaging information
D
Number of Pins NE
Number of Pins ND
A2
A1
D1
P
E
E1
B
Pin 1 A
L
80 A A1 A2 D D1 E E1 L P B ND NE MIN. 2.82 0.25 2.57 23.00 19.90 17.00 13.90 0.65 0.25
LEAD NOM. 3.07 0.35 2.72 23.20 20.00 17.20 14.00 0.75 0.80 0.35 24 16 MAX. 3.32 0.45 287 23.40 20.10 17.40 14.10 0.95 0.45
- 10 -
rev 1.4
I/O Pin Assignment
Pin ID
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Signal
GND NC NC Output Output Output Vcc Output Output Output Output Output Output Output Output Output Output Output GND Output Input Input Vcc Input Input
Designator
Ground
TX3_OUT3 TX3_OUT4 TX4_OUT0 Power TX4_OUT1 TX4_OUT2 TX4_OUT3 TX4_OUT4 -LINK4-(LED) -LED3-(LED) -LINK2-(LED) -LINK1-(LED) -REC4-(LED) -REC3-(LED) -REC2-(LED) Ground -REC1-(LED) LINKOK1 RSCLK1 Power RX1_IN0 RX1_IN1
rev 1.4 - 11 -
I/O Pin Assignment
Pin ID 26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Signal
Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Vdd GND Input Input GNDc Input Input Input Input
Designator
RX1_IN2 RX1_IN3 RX1_IN4 LINKOK2 RSCLK2 RX2_IN0 RX2_IN1 RX2_IN2 RX2_IN3 RX2_IN4 -LINKOK3-RSCLK3RX3IN0 RX3IN1 RX3IN2 RX3IN3 Power (Core) Ground RX3IN4 -LINKOK4Ground (Core) RSCLK4 RX4_IN0 RX4_IN1 RX4_IN2
- 12 -
rev 1.4
I/O Pin Assignment
Pin ID
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
Signal
Input Input Input Input Output N/C Input/Output Vcc GND Input/Output Input/Output Vcc Input/Output Input/Output Input/Output GND Output Output Output Output Output Output Output Vcc Output
Designator
RX4_IN3 RX4_IN4 -RESETLSCLK -DISAB1-(Col) N/C RX_BUSY_0 Power Ground DAISY 0 DAISY 1 Power DAISY 2 DAISY 3 DAISY 4 Ground TX1_OUT0 TX1_OUT1 TX1_OUT2 TX1_OUT3 TX1_OUT4 TX2_OUT0 TX2_OUT1 Power TX2_OUT2
rev 1.4 - 13 -
I/O Pin Assignment
Pin ID Signal Output Output Output Output Output Designator TX2_OUT3 TX2_OUT4 TX3_OUT0 TX3_OUT1 TX3_OUT2
76
77 78 79 80
Clock to Pcolrx inactive at end of collided packet
/dataen <4> /dataen <3> /dataen <2> /dataen <1> /Prxbsy /Pcolrx /Pcol
St0 St0 St0 St0 St0 St0 St0
1F 1F
1>,/Ptxdat<0> 1F
X
1F
1F
1F
/Plsclk Time in ns
St1
00 5 10 15 20
- 14 -
rev 1.4
Clock to Pcolrx and Pcol active when a collision occurs
/dataen <4> /dataen <3> /dataen <2> /dataen <1> /Prxbsy /Pcolrx /Pcol St1 St1 St0 St0 St0 Pu1 HiZ
02
1>,/Ptxdat<0> 03
X
03
03
03
03
X 04
/Plsclk Time in ns
St1
10 5
00
5
10
15
Clock to Prxbsy high and byway data disable at end of packet
/dataen <4> /dataen <3> /dataen <2> /dataen <1> /Prxbsy /Pcolrx /Pcol
St0 St0 St0 St0 St0 Pu1 HiZ
1F 1F
1>,/Ptxdat<0> 1F
X
1F
1F
1F
/Plsclk Time in ns
St1
5 00 5 10 15 20
rev 1.4 - 15 -
Clock to Prxbsy low and by way data enable at beginning of packet
/dataen <4> /dataen <3> /dataen <2> /dataen <1> /Prxbsy /Pcolrx /Pcol St0 St0 St0 St1 Pu1 Pu1 HiZ
1>,/Ptxdat<0> 1F
X 1F
1F
/Plsclk Time in ns
St1
10 5 00 5 10
Clocking of byway data
/dataen <4> /dataen <3> /dataen <2> /dataen <1> /Prxbsy /Pcolrx /Pcol
St0 St0 St0 St1 St0 Pu1 HiZ
0E 0E
1>,/Ptxdat<0> 0E
X 0F
0F
0F
/Plsclk Time in ns
St0
10 5 00 5 10 15
- 16 -
rev 1.4
Beginning of packet (1 channel starts transmission)
/dataen <4> /dataen <3> /dataen <2> /dataen <1> /Prxbsy /Pcolrx /Pcol
St0 St0 St0 St1 St0 Pu1 HiZ
1>,/Ptxdat<0> 1F
X1F
1F 00 01 02 03 04 05 06 07 08 09
XX X XX X X X X X
/Plsclk Time in ns
St1
10 5 00 5 10 15
End of packet (1 channel ends transmission)
/dataen <4> /dataen <3> /dataen <2> /dataen <1> /Prxbsy /Pcolrx /Pcol St0 St0 St0 St0 Pu1 Pu1 HiZ
1A X X1BX1C 1D 1EX X01X02X03 04X05X06X1F X X X 1F 1F
1>,/Ptxdat<0> 1F
X 1F
/Plsclk Time in ns
St1
25 20 15 10 5 00 5
rev 1.4 - 17 -
Beginning of collision (two channels try to transmit simultaneously)
/dataen <4> /dataen <3> /dataen <2> /dataen <1> /Prxbsy /Pcolrx /Pcol
St0 St0 St0 St0 Pu1 Pu1 HiZ
1F
1>,/Ptxdat<0> 1F
X 1F
1F 00 01 02 03 04 05 06
0B X X X X X X X X07X08 09X0AX X X
/Plsclk Time in ns
St1
25 20 15 10 5 00 5
End of collision (the collided channels ceased transmission)
/dataen <4> St0 /dataen <3>
St0 /dataen <2> St0 /dataen <1> St0 1>,/Ptxdat<0> 1F /Prxbsy Pu1 /Pcolrx Pu1 /Pcol HiZ
X XX X X X X X07 08 09 0A 0B 0C 0DX0E 1F
X1FX1F 1F X
1F
/Plsclk St1 Time in ns
25
20
15
10
5
00
5
- 18 -
rev 1.4
Electrical Specification Vcc Vdd (Core) Icu GND and GNDc Input - Low Input - High Output - Low Output - High Input - Load LSCLK +5V 10% +5V 10% 50 mA (typical) 60 mA (max) 0V < 0.7V 1.8V < 0.6V 2.6V 5 gates 25 Mhz
Operating Temperature: Range 0C - 70C Humidity 90% (Non condensing) Storage Temperature: Range -10C - +80C Humidity 95% (Non condensing) Product has to be used within 6-7 hours after unpacking.
rev 1.4 - 19 -
AB Semicon Inc. 8305 Highway 71 West Austin Texas 78735 USA Tel: +1 512 288 6750 Fax: +1 512 288 7676
Distributed in Japan Rikei Corporation 1-26-2 Nishi-Shinjuku Shinjuku-Ku Tokyo 163-05 Japan Tel: +81 3 3345 2189 Fax: +81 3 3344 3949
AB Semicon Limited AB Semicon House 62 Victoria Road Burgess Hill West Sussex RH15 9LH Tel: +44 1444 870408 Fax: +44 1444870452 www.ab-semicon.com

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